AMD Launches CDNA5 GPU Architecture, Rebases on RDNA for AI Workloads

At AMD's Advancing AI 2026 event, the company unveiled CDNA5, the next-generation architecture for its Instinct line, including the MI455 and Helios GPUs. Alan Smith, AMD's Corporate Fellow and Chief Architect for Datacenter GPUs, walked through the design with interviewer George, explaining the reasoning behind a major architectural rebasing and several key microarchitectural changes.

The most significant decision was moving away from GCN, a lineage stretching back to 2012's Tahiti, and rebasing CDNA5 on RDNA. Smith cited multiple motivations: bringing a modern execution engine, improving the cache system, and—importantly—unifying the gaming and data-center GPU roadmaps so that optimizations in one domain could benefit the other. With AI now permeating not just data centers but also gaming rendering and neural upscaling, Smith argued that a shared foundation allowed AMD to "bring that together and leverage them on both product lines."

At the execution level, CDNA5 shifts from four SIMD16 units (each handling one Wave64 instruction every four cycles) to four SIMD32 units (each handling one Wave32 instruction per cycle). CDNA5 deprecates Wave64 support, despite RDNA retaining it. Smith explained that Wave64 carried overhead—branch divergence and register pressure penalties—that, in most real-world workloads according to AMD's profiling, made Wave32 the better choice. This change is paired with a near-quadrupling of per-wave VGPR addressing: from 256 VGPRs to 1024 VGPRs, reducing register pressure and improving occupancy.

The cache hierarchy underwent radical redesign. Previous CDNA generations used an L1 cache private to each CU, an L2 cache per XCD (a cluster of CUs), and an Infinity Cache (memory-side) as a final level. CDNA5 replaces this with two client-side L2 caches on the base dies, each serving eight shader engines from one accelerator complex die. Smith described three design goals: (1) enabling global (die-scope) atomic operations with higher throughput by moving them into the L2; (2) eliminating the kernel-boundary flush previously required on the L2 for global visibility in the MI350 series; and (3) increasing global memory bandwidth by avoiding cross-chiplet traversal for L2 accesses. The interface between the two L2 caches is 14 TB/s bi-directional, sized to sustain full HBM bandwidth in NPS1 (single-package scaling) mode while carrying coherency traffic—a design analogous to how EPYC manages L3 coherency.

For the WGP (workgroup processor), CDNA5 splits the 384-kilobyte cache into 320 kilobytes of LDS (local data share) and 64 kilobytes of vector data cache. Although the architecture supports programmable splits, MI455 uses a fixed configuration; Smith noted that the larger LDS is the right balance for high tensor throughputs. Other SKUs—notably the MI430—may employ different splits.

To support both HPC and AI workloads, AMD employed its chiplet architecture to create two optimized compute variants. Both share the same control logic, register file bandwidth, scheduling, and vector ALUs. The difference lies in numerics: the HPC variant includes full double-precision floating-point units for traditional simulation codes requiring IEEE 64-bit compliance, while the AI variant maximizes throughput for vector and tensor operations. This approach allowed AMD to tailor the SIMD implementations to each use case without maintaining two entirely separate architectures.

CDNA5 represents a strategic pivot for AMD's data-center GPU roadmap. Rather than continue layering optimizations atop the GCN architecture that had served since 2012, AMD chose to rebase on RDNA—the architecture powering its consumer and gaming GPUs—to realize long-term gains in code reuse, shared optimization, and design efficiency. Alan Smith, AMD's Corporate Fellow and Chief Architect for Datacenter GPUs, emphasized that AI is now ubiquitous, present not only in data centers but also in gaming rendering and neural upscaling; a unified architecture allows both product families to benefit from algorithmic advances in one domain.

The architectural overhaul is deep. The shift from Wave64 to Wave32 execution, combined with a doubling of per-wave VGPR addressing (256 to 1024), reflects AMD's analysis that Wave32 workloads dominate real-world profiling traces and offer better common-case performance despite losing some narrow optimization opportunities available on Wave64. The cache redesign—moving from a distributed L1-per-CU and memory-side Infinity Cache to a pair of large client-side L2 caches, each shared by eight shader engines—was driven by three concrete goals: enabling global atomic operations with higher throughput, eliminating costly kernel-boundary flushes on the L2, and increasing global memory bandwidth by reducing cross-chiplet latency. The die-to-die link is sized to sustain full HBM bandwidth and coherency traffic simultaneously, mirroring the cache-coherency approach EPYC uses across its L3 caches.

AMD's use of chiplet variants—a single base architecture split into HPC and AI-optimized compute dies—reflects confidence in the underlying CDNA5 design while acknowledging that the two workload classes have different numeric precision needs. This modular approach sets up potential flexibility for future SKUs, though the MI455 ships with fixed cache splits optimized for AI tensor throughput.