UALink Consortium releases major update to AI accelerator interconnect standard, adding in-network compute and chiplet specifications

UALink Common Specification 2.0 was released less than a year after UALink 1.0 (released in April 2025). The update adds in-network compute capabilities, which allow computation and communication between accelerators while reducing latency and bandwidth usage. The link layer and physical layer have been separated to enable independent updates to physical interfaces and speeds.

A new UALink Manageability Specification 1.0 introduces centralized control and management planes. A UALink chiplet specification developed with the UCIe consortium defines how to integrate UALink technology into chiplet-based systems (modular processor designs), including interfaces, form factors, and chiplet management standardization.

According to Kurtis Bowman, UALink consortium board chair, the interconnect is strategic because it determines 'how fast you're going to be able to get your tokens, how fast you can do your training, how fast you can do your inference.' Peter Onufryk, UALink Consortium president, stated the standard was designed as a 'ground-up implementation that's optimized' for scale-up AI fabrics (large distributed AI systems).

A compliance specification will be released later in 2026, and the consortium will hold a plugfest to ensure compatibility across switches and accelerators.