AMD begins production ramp of 6th Gen EPYC processor 'Venice' on TSMC 2nm technology, marking first HPC product to achieve this milestone

AMD announced on May 21, 2026, that its next-generation AMD EPYC processor codenamed 'Venice' is ramping production in Taiwan on TSMC's 2nm process technology, with future plans to ramp production at TSMC's Arizona facility.

'Venice' is the first high-performance computing (HPC) product in the industry to enter production on TSMC's advanced 2nm process technology, delivering leadership performance and energy efficiency for cloud, enterprise, and AI infrastructure.

The ramp reflects growing customer demand for EPYC processors to power cloud, enterprise, HPC, and AI deployments as agentic workloads (self-directing AI systems) scale, requiring CPUs to coordinate data movement, networking, storage, security, and system orchestration across data centers.