AIToday
AI Business & IndustryDIGITIMES AsiaPublished: Aug 12, 2026, 10:01 JST

TSMC cuts 3D chip development cycle to one year, tackles material risks

TSMC cuts 3D chip development cycle to one year, tackles material risks

TSMC is shortening its 3D integrated circuit (3DIC) development cycle to one year while addressing material reliability challenges in its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technology, according to Dr Jun He, TSMC's vice president of Advanced Packaging Technology and Service and Corporate Quality and Reliability.

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