AI chip power shifts force earlier data-center design input, Cadence says

Cadence Design Systems highlights a rising challenge for data-center builders. AI accelerators now shift power and heat demands quickly. This forces earlier collaboration between chip and facility engineers.

Ikemoto's comment points to a planning shift, not just a technical tweak. Designers must merge chip-level data into early layout stages. This could affect project timelines and budgets, though Cadence does not specify details.

Still, the company's stance suggests a growing overlap between semiconductor design and infrastructure. Data-center teams may need new workflows to keep up with chip evolution. Cadence, as an EDA vendor, likely sees this as an opportunity, though the article does not state that.