AIToday
AI Business & IndustryDIGITIMES AsiaPublished: Sep 5, 2026, 06:03 JST1 min read

K&S expands advanced packaging roadmap for CPO, CoPoS growth

K&S expands advanced packaging roadmap for CPO, CoPoS growth

Key takeaway

  • K&S has expanded its TCB advanced packaging roadmap.

  • The company targets CPO and CoPoS growth.

  • This addresses emerging chip integration needs in AI systems.

3 Key Points

  1. What happened

    K&S (Kulicke and Soffa) has expanded its TCB (thermal compression bonding) advanced packaging roadmap, targeting growth in CPO (co-packaged optics) and CoPoS (chip-on-package-on-substrate) applications.

  2. Why it matters

    This move positions K&S to address emerging advanced packaging demands, where TCB is a key technology for integrating chiplets and optical components in high-performance computing and AI systems.

  3. What to watch

    The roadmap's success will likely depend on adoption rates of CPO and CoPoS architectures in next-generation data center and AI accelerator designs.

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Context & Analysis

K&S's expanded TCB roadmap responds to growing complexity in advanced packaging. Traditional packaging methods face limits as chip designs incorporate more heterogeneous components. TCB offers finer pitch connections needed for integrating chiplets and photonics. CPO and CoPoS represent next-generation approaches. CPO aims to bring optics closer to compute to improve bandwidth and power efficiency. CoPoS addresses the challenge of stacking multiple dies with high interconnect density. K&S's focus on these areas suggests the company expects demand to rise alongside AI infrastructure buildouts. Success depends on industry adoption of these architectures, which could shape future packaging equipment demand.

FAQ

What are CPO and CoPoS?
CPO refers to co-packaged optics, integrating optical components with chips. CoPoS refers to chip-on-package-on-substrate, a packaging architecture for stacking chiplets.
What is TCB?
TCB stands for thermal compression bonding, a method used in advanced semiconductor packaging to connect chips with high precision and density.
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