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d-Matrix pairs custom chips with NVIDIA GPUs for faster AI token generation

SiliconANGLE AI2d ago
d-Matrix pairs custom chips with NVIDIA GPUs for faster AI token generation

Key takeaway

d-Matrix has announced a production deployment pairing its custom Corsair accelerators with NVIDIA's GPUs to speed up AI token generation — the step where an AI produces each word of output. Fast token generation now commands premium pricing up to 10x higher than standard tokens, creating new revenue for cloud providers. The partnership represents a shift from GPU-only infrastructure to heterogeneous hardware, with d-Matrix's chips optimized for memory bandwidth rather than raw compute.

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3 Key Points

  • What happened

    d-Matrix announced a production deployment of its Corsair accelerators paired with NVIDIA Hopper and Blackwell GPUs — described as one of the first commercial-scale examples of heterogeneous disaggregated inference in production. The setup separates compute-heavy prefill operations from latency-sensitive decode operations, with d-Matrix's custom hardware optimized for the latter.

  • Why it matters

    Fast token generation (the step where an AI produces each word of output) now commands premium pricing — as much as 10x higher than standard throughput tokens — creating a new revenue opportunity for inference providers. Agentic AI use cases and demand for real-time interactivity are driving inference providers to move beyond GPU-only infrastructure, making memory bandwidth the bottleneck rather than raw compute power.

  • What to watch

    d-Matrix is developing a next-generation 3D architecture that will stack four DRAM layers directly on top of compute logic on a single substrate, aiming to deliver higher capacity and bandwidth in a smaller footprint to produce more fast tokens.

Context & Analysis

The announcement reflects a fundamental shift in how inference infrastructure is being architected. For months, the focus in AI has been on training speed and model size, but as agentic AI use cases move into production and users demand real-time interactivity, the bottleneck has moved to inference — and specifically to the latency of token generation, the step where an AI produces each successive word of output. The economics are clear: inference providers can charge substantially more (up to 10x) for fast tokens, creating a new revenue tier that makes optimized hardware a business imperative, not just a performance nice-to-have.

The technical insight driving this shift is that AI inference is no longer limited by raw compute power (floating-point operations per second). Instead, it is bottlenecked by memory bandwidth — how fast data can move between memory and the logic that processes it. GPU-only infrastructure, optimized for high compute throughput, does not address this constraint. d-Matrix's Corsair platform solves it by integrating DRAM and compute logic on a single substrate, shrinking the physical distances data must travel and dramatically improving bandwidth per unit of energy. The partnership with NVIDIA — pairing Corsair with Hopper and Blackwell GPUs — represents a pragmatic acknowledgment that different hardware is needed for different parts of the inference pipeline, and that heterogeneous architectures may become the standard blueprint for production inference clouds. The next generation, stacking four DRAM layers on top of compute, suggests d-Matrix is betting that this trend will intensify as demand for fast tokens grows.

FAQ

What is heterogeneous inference and why does it matter?
Heterogeneous inference separates AI workloads into two distinct phases: compute-heavy prefill and latency-sensitive decode. By pairing different hardware optimized for each phase — NVIDIA GPUs for prefill and d-Matrix Corsair accelerators for decode — inference providers can achieve faster token generation, which currently commands premium pricing up to 10x higher than standard throughput tokens.
How does d-Matrix's Corsair hardware achieve faster token generation?
Corsair stacks DRAM and compute logic together on a single substrate, delivering memory bandwidth well beyond what high-bandwidth memory (HBM) architectures can achieve. By reducing the physical distance data must travel between memory and logic, the platform achieves many times the performance of HBM memory while consuming very low energy.
What is d-Matrix's next step?
d-Matrix is developing a next-generation 3D architecture that will stack four DRAM layers directly on top of compute logic, aiming to increase capacity and bandwidth in a smaller footprint to produce more fast tokens.

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