JEDEC releases cheaper AI memory standard with 512-bit interface

JEDEC's release of SPHBM4 addresses a real constraint in AI accelerator design: the cost and manufacturing bottleneck created by ultra-wide memory interfaces and advanced packaging. Conventional HBM4 and HBM4E use 1024-bit or 2048-bit interfaces, which consume significant chip area, require expensive interposers, and depend on scarce advanced packaging capacity at foundries like TSMC. SPHBM4 converts the internal 2048-bit HBM4 interface into a 512-bit external channel by introducing a sophisticated PHY (physical-layer controller) that serializes the data and boosts the data rate to between 22.4 and 46.0 GT/s per pin, offsetting the narrower interface.

The trade-offs are real: SPHBM4 introduces additional latency through its SerDes-like PHY, falls short on peak bandwidth, and may face power-efficiency challenges because high-speed narrow data transfer is inherently less efficient than slow wide parallel transfer. For flagship AI accelerators seeking maximum performance, HBM4 and HBM4E will remain the standard. However, for a broader class of applications where cost matters more than marginal bandwidth gains, SPHBM4 opens a new segment. The use of standard organic substrates and the elimination of interposers should lower total integration cost, even if SPHBM4 still requires sophisticated base-die engineering.

The China angle is particularly notable: developers like Biren, Huawei, and Moore Threads, who are blocked from TSMC packaging services, stand to benefit disproportionately. SPHBM4's compatibility with standard substrates aligns with existing Chinese packaging infrastructure. Yet the critical bottleneck remains: only Samsung, SK hynix, and Micron can make HBM4 DRAM stacks, and China's CXMT can barely produce HBM2E. Until Chinese memory makers develop competitive HBM4 production, SPHBM4 advantage for Chinese accelerator makers will remain constrained.