Nvidia Deploys AI Agents to Accelerate Chip Design as Complexity Outpaces Traditional Methods

Nvidia has long positioned itself as the central engine of AI infrastructure, from GPUs and CPUs to CUDA-X libraries and Nemotron models. But as chip complexity accelerates, the company is applying that same AI-first philosophy to the problem of designing chips themselves. Tim Costa, vice president and general manager of computational engineering at Nvidia, laid out the challenge in stark terms: by 2030, the semiconductor industry is projected to produce 2 trillion chips and process about 41 million wafers each month. Individual packages are approaching a trillion transistors, and entire computing systems will reach transistor counts in the quadrillions. Traditional chip design—simulation, verification, implementation—takes years, a timeline incompatible with the pace of AI-driven hardware demands.

The core insight is that this complexity is not one-dimensional. "The key point is not any one number; it's the interaction of scale, architecture, packaging, and system complexity," Costa explained. Decisions in chip architecture cascade through atomic-scale manufacturing, advanced packaging, power, thermals, and system behavior. AI helps engineers explore far more design alternatives and make better decisions across those interactions; accelerated computing makes the high-fidelity simulation, validation, and optimization fast enough to repeat. Rather than replacing physics or design rules, AI puts domain-specific checks into the loop and lets engineers use them more often, accelerating the full engineering loop rather than isolated tools.

To operationalize this vision, Nvidia is deploying Vera—an Arm-based CPU featuring 88 custom Olympus cores designed by Nvidia and a 1.2 TB/sec LPDDR5X memory subsystem—across the electronic design automation (EDA) workflows of Cadence and Synopsys. Early testing shows Vera running on Synopsys's VCS and Cadence's Jasper platforms delivers 1.5 times the performance of AMD's Epyc Torrent systems, with practical benefits in shorter simulation and verification runs and faster iteration. Nvidia is using Vera itself to help design Rosa, its next-generation CPU built on the Rigel core, scheduled to launch in 2028 as part of the Feynman datacenter platform.

The broader industry is moving in parallel. Cadence announced AI Super Agent in February for silicon design and verification, followed by partnerships with Nvidia, TSMC, and Google around agentic chip and system design. Last month, Cadence launched AuraStack AI Super Agent for front-end agentic workflows. According to Cadence, its AI Super Agents can implement hundreds of simulations in less than a day—work that currently requires five weeks—delivering 40-times faster Register-Transfer Level (RTL) validation cycles. Synopsys, meanwhile, announced this week agentic AI partnerships with AMD, Microsoft, and Intel alongside Nvidia. At the Design Automation Conference in California, Synopsys demonstrated its Fully Autonomous Design Verification Workflow, built on its agentic platform and AgentEngineer technology and incorporating Nvidia technologies including Nemotron 3 Ultra, Agent Toolkit, and OpenShell runtime. The vendor claims it can deliver validated RTL 50 times faster than other platforms.

On the software side, Nvidia is expanding its Agent Toolkit—launched in March with Nemotron models and OpenShell runtime, and later augmented with Nemotron 3 Ultra, an open model for agentic coding in chip design. The toolkit now includes a rearchitected PhysicsNeMo, shifting from a manual framework for experts to an open, composable set of libraries with agent-ready skills. These libraries cover practical layers and engineering workflow needs, physics-aware operations, GPU-native mesh processing, distributed training, and data curation—skills that encode repeatable instructions for tasks like model acceleration, training configuration, data pipeline creation, and dataset curation, specifying which tools to call, what outputs to produce, and how results should be checked. CUDA-X, Nvidia's acceleration library suite, now includes cuISS for large sparse linear systems in physics and engineering simulations on GPUs, complementing existing tools like cuDSS for direct sparse solvers and cuEST for quantum chemistry. The shift, Costa said, is "from a framework an expert operates manually to AI physics capabilities an agent can invoke, compose, and validate inside a larger engineering process."

Nvidia's push into AI-driven chip engineering reflects a structural break in the semiconductor industry: the complexity of future hardware now outpaces what human-led design workflows can deliver on schedule. Tim Costa, Nvidia's vice president of computational engineering, framed the challenge plainly—by 2030 the industry must produce 2 trillion chips and process about 41 million wafers monthly while individual packages approach a trillion transistors and entire systems reach quadrillions. Traditional simulation, verification, and implementation steps take years; in the accelerated age of AI, that timeline is untenable. The shift is not marginal optimization but foundational: AI moves from being a productivity tool to becoming the engineering infrastructure itself.

What makes this meaningful is how the industry is acting on it in lockstep. Both Cadence and Synopsys—the dominant electronic design automation vendors—have launched agentic platforms (AI Super Agent and Fully Autonomous Design Verification Workflow, respectively) within months of each other, and both are working with Nvidia, AMD, Microsoft, Intel, TSMC, and Google. The numbers are striking: Cadence's agent cuts five weeks of work to less than a day by running hundreds of simulations in parallel; Synopsys's workflow delivers validated RTL 50 times faster. These are not incremental gains but orders-of-magnitude leaps.

Nvidia's own deployment is a proof point. Vera—the custom CPU Nvidia designed for chip design itself—is now running across Cadence and Synopsys workflows to help design Rosa, Nvidia's next-generation CPU due in 2028. By using its own hardware and agents to design its future chips, Nvidia signals that agentic design is not aspirational but already embedded in the critical path. The PhysicsNeMo rearchitecture and CUDA-X expansions (cuDSS, cuEST, cuISS) reflect a deeper shift: moving from frameworks that experts operate manually to agent-ready libraries that can invoke, compose, and validate inside larger workflows. This is infrastructure scaling, and it is happening now.

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