New AI agent UCAgent aims to automate semiconductor verification, which currently consumes 70% of IC development time

Functional verification is a critical bottleneck in semiconductor development, accounting for approximately 70% of total project time

Traditional verification methods like constrained-random and formal verification struggle with the complexity of modern chip designs

UCAgent addresses three key challenges: improving accuracy in generating Verilog/SystemVerilog code, enhancing reliability of multi-step workflows, and maintaining consistency across specifications and test cases

The proposed end-to-end agent leverages advances in Large Language Models to automate the verification process and reduce development cycles