Synopsys has unveiled fully autonomous AI agents for chip design and thermal simulation, built in collaboration with NVIDIA, that accelerate chip verification by up to 50X while improving coverage by 20%. The agents autonomously handle setup, analysis, and post-processing tasks that previously required weeks of manual work, compressing them into hours. This represents a shift toward agentic AI in engineering—where AI agents reason and execute entire workflows independently—promising significant productivity gains for R&D teams across silicon and systems development.
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Synopsys announced fully autonomous AI agents for chip design and thermal simulation, built with NVIDIA Nemotron technology. The chip verification agent delivers up to 50X faster time-to-validated RTL while achieving 20% additional coverage improvement; a new thermal-management workflow automates setup, preprocessing, and post-processing. The company also expanded its portfolio to more than 20 GPU-accelerated EDA and multiphysics products, including an 18X speedup for PrimeSim SPICE simulations.
Why it matters
Agentic AI—agents that reason, plan, and execute complex workflows autonomously—shifts engineering from manual, time-consuming tasks to automated insight generation. By collapsing chip verification cycles and compressing thermal analysis from weeks to hours, these tools address a critical bottleneck in product development. For R&D teams, the productivity multiplier could meaningfully shorten time-to-market and reduce engineering labor intensity.
What to watch
Synopsys demonstrated these capabilities for the first time at the 2026 DAC Chips to Systems Conference on July 26, 2026. The partnership between Synopsys and NVIDIA—combining Synopsys' domain expertise in EDA and CAE with NVIDIA's accelerated computing platform and runtime security—signals deepening collaboration in agentic engineering tools.
At the 2026 DAC Chips to Systems Conference on July 26, 2026, Synopsys announced a suite of autonomous AI agents for chip and systems design built in partnership with NVIDIA. The centerpiece is a fully autonomous chip verification agent that orchestrates the entire verification cycle—a traditionally labor-intensive phase where engineers manually validate designs against specifications. This agent achieves up to 50X faster time-to-validated RTL (Register Transfer Language) while simultaneously improving coverage by 20%, a quality metric in verification. Synopsys also demonstrated its first fully autonomous CAE (computer-aided engineering) workflow for thermal management and cooling of electronic devices, automating the setup, preprocessing, and post-processing steps that previously consumed significant manual effort. The technology leverages NVIDIA Nemotron—a large language model optimized for domain tasks—running on NVIDIA's accelerated computing hardware and protected by NVIDIA OpenShell runtime. Beyond the flagship agents, Synopsys expanded its product portfolio to include more than 20 GPU-accelerated EDA and multiphysics tools, with PrimeSim SPICE simulations achieving an 18X speedup. According to Tim Costa, Vice President and General Manager for Computational Engineering at NVIDIA, the shift compresses development cycles "from weeks to hours," reflecting how agentic workflows can reason, plan, and execute complex tasks across the entire product lifecycle while verifying their own work. Synopsys Chief Product Management Officer Ravi Subramanian emphasized that the partnership combines Synopsys' deep domain expertise in EDA and CAE with NVIDIA's AI infrastructure and accelerated computing, positioning the company to build the next generation of autonomous engineering tools.
Synopsys' announcement reflects a broader shift in engineering software toward agentic AI—systems where autonomous agents plan and execute complex, multi-step workflows without constant human intervention. The collaboration with NVIDIA underscores how domain expertise (Synopsys' EDA and CAE tools) and AI infrastructure (NVIDIA's accelerated compute and Nemotron language model) are combining to unlock new capabilities. The 50X speedup in chip verification and the automation of thermal simulation represent tangible compression of cycles that have long been bottlenecks in semiconductor and electronics design. By compressing development timelines from weeks to hours, these tools promise to reshape how engineering teams allocate labor and manage project schedules, making faster iteration and deeper analysis feasible within the same calendar window.
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