TOPCELL uses large language models to optimize transistor layouts in advanced semiconductor chips, outperforming traditional exhaustive search methods at 2nm nodes.

TOPCELL reformulates transistor topology optimization as a generative task using LLMs instead of conventional computationally expensive exhaustive search methods

The framework employs Group Relative Policy Optimization (GRPO) to fine-tune models while respecting circuit logic and layout spatial constraints

Experimental results on 2nm technology nodes show TOPCELL discovers routable, physically-aware topologies that surpass foundation models

Addresses a critical bottleneck in standard cell design by improving diffusion sharing efficiency and downstream routability