Cadence announces Level-5 autonomous AI design engineer for chip verification, delivering over 40X faster RTL validation cycles and reducing typical five-week verification loops to less than a day.

Cadence extended its ChipStack AI Super Agent to Level-5 autonomy at Computex 2026, enabling fully autonomous virtual agentic AI design engineers built on Cadence's AI-driven electronic design automation portfolio with NVIDIA Nemotron models and secured by NVIDIA OpenShell runtime.

The autonomous agent independently executes complex chip design and verification workflows—including specification understanding, RTL generation, verification planning, formal analysis, simulation, debug and design convergence—while allowing engineers to inspect, guide and collaborate as needed.

At NVIDIA, the system enables each engineer to run hundreds of dynamic simulations with Cadence Xcelium Logic Simulation and Jasper Formal Verification, reducing verification cycles that traditionally took weeks to less than a day in leading-edge deployments and delivering over 40X faster RTL validation cycles.