Same chip, same model: 134.7 ms vs 5.03 ms on Qualcomm Dragonwing RB3 Gen 2

A model which appears to run may be quietly executing most of its network on GPU and CPU. In the default TFLite path, only 19 of 343 layers ran on the NPU, while 168 layers went to the GPU and 156 to the CPU. Without a layer-by-layer profile, one would record 134.7 ms as the chip's performance and never see the misplacement.

The failures are equally instructive. A precompiled FP32 model was rejected because the device demands quantized I/O. A w8a16 QDQ conversion returned only exit code 14, prompting an upstream issue at qualcomm/ai-hub-models#364. A QNN DLC FP32 model compiled but failed on-device with MODEL_GRAPH_ERROR, a reminder that compilation success is not execution success.

The Galaxy S25 control run matters because it isolates the problem: on a flagship phone, even the default TFLite delegate placed all layers on the NPU at about 2.9 ms. The author notes the same failure pattern on Rockchip boards, where RKNN models silently fall back to CPU per operator. The takeaway is that a latency figure without its runtime, precision, and layer placement is incomplete, and layer profiles are the only evidence that distinguishes a slow NPU from an NPU that was never given the work.