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Powertech, Broadcom form $400M Singapore FOPLP joint venture

DIGITIMES Asia2h ago
Powertech, Broadcom form $400M Singapore FOPLP joint venture

Key takeaway

Powertech Technology and Broadcom have formed a joint venture in Singapore backed by US$400 million(約640億円) in planned investment to build panel-level advanced packaging capacity. Panel-level packaging is a manufacturing technique that increases chip output per wafer, reducing costs for AI processors. The move reflects both companies' commitment to FOPLP as a strategic technology for producing AI ASICs.

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3 Key Points

  • What happened

    Powertech Technology's board approved a joint venture with Broadcom in Singapore to build panel-level advanced packaging (PLP) manufacturing capacity, with planned investment totaling US$400 million(約640億円).

  • Why it matters

    Panel-level packaging allows semiconductor makers to produce more chips per wafer, lowering costs for AI processors and other advanced chips. This partnership signals both companies are betting on FOPLP (fan-out panel-level packaging) as a key manufacturing technology for AI ASICs (application-specific integrated circuits).

  • What to watch

    The venture will expand Powertech's panel-level packaging strategy in Singapore, positioning the company to serve growing demand for AI chip manufacturing capacity alongside its existing operations.

In Depth

Powertech Technology announced that its board has approved the formation of a joint venture with Broadcom in Singapore focused on panel-level advanced packaging (PLP) manufacturing. The venture is planned to invest a total of US$400 million(約640億円) to build manufacturing capacity for FOPLP (fan-out panel-level packaging), a technology that enables semiconductor makers to produce more chips per wafer, thereby reducing costs for AI processors and other high-demand chips. The move represents a deepening of Powertech's existing panel-level packaging strategy. By partnering with Broadcom—a major semiconductor company with significant expertise in chip design and manufacturing—and locating the venture in Singapore, Powertech is positioning itself to capture growth opportunities in AI ASIC production while leveraging the cost advantages of panel-level packaging technology.

Context & Analysis

Powertech Technology is reinforcing its position in advanced semiconductor packaging through this strategic partnership with Broadcom. The joint venture represents a significant capital commitment—US$400 million(約640億円) in planned investment—underscoring the importance both companies place on FOPLP as a manufacturing solution. Panel-level advanced packaging is a competitive advantage in an environment where AI chip demand continues to grow; by securing dedicated manufacturing capacity in Singapore, Powertech and Broadcom are positioning themselves to serve this demand while reducing production costs through higher chip yields per wafer. The venture deepens Powertech's existing panel-level packaging strategy, indicating the company sees this as a core competency for the years ahead.

FAQ

Where will this manufacturing facility be located?
The joint venture will be based in Singapore.
What is panel-level packaging used for?
Panel-level packaging allows semiconductor makers to produce more chips per wafer, which lowers costs for AI processors and other advanced chips.

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